The embodiments of the invention relate generally to the fabrication of semiconductor devices and more particularly to the fabrication of dual gate stacks of a CMOS structure having two different channel materials on a common semiconductor substrate.
Leading edge Si CMOS industry is facing strong limitations with Si for 10 nm node and beyond. One promising approach to achieving sub-10 nm geometry devices is co-integration of SixGe1-x (where x=0 to 1) p-FETs with group III-V compound n-FETs.
Scaling the gate stack and obtaining high-quality gate stacks are particular challenges.
High-k gate dielectrics are used to scale down the equivalent oxide thickness of the gate dielectric while controlling gate leakage. However, dual CMOS gate stacks on SixGe1-x and group III-V compound materials require different interface materials between the channel materials and the gate stack.